HMP112S6EFR6C-S5 - 200pin Unbuffered DDR2 SDRAM SO-DIMMs

This page provides the datasheet information for the HMP112S6EFR6C-S5, a member of the HMP164S6EFR6C-C4 200pin Unbuffered DDR2 SDRAM SO-DIMMs family.

Product Overview

Hynix

Part number	HMP112S6EFR6C-S5
Manufacturer	Hynix
File Size	547.93 KB
Description	200pin Unbuffered DDR2 SDRAM SO-DIMMs
Datasheet	HMP112S6EFR6C-S5 Datasheet
Additional preview pages of the HMP112S6EFR6C-S5 datasheet.

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

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JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply.
All inputs and outputs are compatible with SSTL_1.8 interface.
Posted CAS Programmable CAS Latency 3,4,5, and 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination).
Fully differential clock operations (CK & CK).
Programmable Burst Length 4 / 8 with both sequential and interl.

Other Datasheets by Hynix

Published: Dec 12, 2013 |