Description
The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits.
Internally configured as a quad-bank DRAM with a synchronous interface.
Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits.
Features
- Clock frequency: 200, 166, 143, 133 MHz.
- Fully synchronous; all signals referenced to a positive clock edge.
- Internal bank for hiding row access/precharge.
- Single 3.3V power supply.
- LVTTL interface.
- Programmable burst length.
- (1, 2, 4, 8, full page).
- Programmable burst sequence: Sequential/Interleave.
- Self refresh modes.
- Auto refresh (CBR).
- 4096 refresh cycles every 64 ms (Com, Ind, A1 grade) or 1.
IS42S16400J Datasheet
