Datasheet4U Logo Datasheet4U.com

IS61LV6464 - 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM

General Description

static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors.

It is organized as 65,536 words by 64 bits, fabricated with ISSI's advanced CMOS technology.

Key Features

  • Fast access time:.
  • -100 MHz; 6 ns-83 MHz.
  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Pentium™ or linear burst sequence control using MODE input.
  • Five chip enables for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • Power-down control by ZZ input.
  • JEDEC 128-Pin TQFP 14mm x 20mm p.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
IS61LV12816 128K x 16 HIGH-SPEED CMOS STATIC RAM Integrated Circuit Solution
IS61LV12816 128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY Integrated Silicon Solution
IS61LV12816L 128K x 16 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61LV12816LL 128K x 16 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61LV12824 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61LV6416 64K x 16 HIGH-SPEED CMOS STATIC RAM
IS61LV6416L 64K x 16 HIGH-SPEED CMOS STATIC RAM
IS61LV12816 128K x 16 HIGH-SPEED CMOS STATIC RAM
IS61LV25616 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM
IS61LV25616L 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61LV6464 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM FEATURES • Fast access time: – -100 MHz; 6 ns-83 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Five chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 128-Pin TQFP 14mm x 20mm package • Single +3.3V power supply • 2.