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IS61QDB24M18 - QUAD (Burst of 2) Synchronous SRAMs

Download the IS61QDB24M18 datasheet PDF. This datasheet also covers the IS61QDB22M36 variant, as both devices belong to the same quad (burst of 2) synchronous srams family and are provided as variant models within a single manufacturer datasheet.

General Description

The 72Mb IS61QDB22M36 and IS61QDB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Key Features

  • 2M x 36 or 4M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Separate read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with early write operation.
  • Double data rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDB22M36-ISSI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for IS61QDB24M18 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IS61QDB24M18. For precise diagrams, and layout, please refer to the original PDF.

72 Mb (2M x 36. & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • S...

View more extracted text
18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with early write operation. • Double data rate (DDR) interface for read and write input ports. • Fixed 2-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Two input clocks (C and C) for data output control. • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • H

More Datasheets from ISSI (now Infineon)

Part Number Description
IS61QDB24M18A 72Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB21M18A 18Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB21M18C 18Mb QUAD Synchronous SRAM
IS61QDB21M36 QUAD (Burst of 2) Synchronous SRAMs
IS61QDB21M36A 36Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB21M36C 36Mb QUAD Synchronous SRAM
IS61QDB22M18 QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M18A 36Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB22M18C 36Mb QUAD Synchronous SRAM
IS61QDB22M36 QUAD (Burst of 2) Synchronous SRAMs