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IS61QDP2B41M18A1 - 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM

This page provides the datasheet information for the IS61QDP2B41M18A1, a member of the IS61QDP2B41M18A 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM family.

Datasheet Summary

Description

512Kx36 and 1Mx18 configuration available.

valid window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) inter

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Datasheet Details

Part number IS61QDP2B41M18A1
Manufacturer ISSI
File Size 647.33 KB
Description 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
Datasheet download datasheet IS61QDP2B41M18A1 Datasheet
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Full PDF Text Transcription

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IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2 1Mx18 , 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.0 Cycle Read Latency) OCTOBER 2014 FEATURES DESCRIPTION  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support. The 18Mb IS61QDP2B451236A/A1/A2 and IS61QDP2B41M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices.
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