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IS61QDP2B41M18C - 18Mb QUADP SYNCHRONOUS SRAM

General Description

1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interfa

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDP2B41M18C1 18Mb QUADP SYNCHRONOUS SRAM
IS61QDP2B41M18C2 18Mb QUADP SYNCHRONOUS SRAM
IS61QDP2B41M18A 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B41M18A1 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B41M18A2 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61QDP2B41M18C/C1/C2 IS61QDP2B451236C/C1/C2 1Mx18, 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.0 Cycle Read Latency) APRIL 2016 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid Pin (QVLD).  +1.8V core power supply and 1.5, 1.