IS61QDP2B41M18C1 Datasheet PDF - ISSI 18Mb QUADP SYNCHRONOUS SRAM Specs

IS61QDP2B41M18C1 - 18Mb QUADP SYNCHRONOUS SRAM

This page provides the datasheet information for the IS61QDP2B41M18C1, a member of the IS61QDP2B41M18C 18Mb QUADP SYNCHRONOUS SRAM family.

Datasheet Summary

Description

1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interfa

Datasheet Details

Part number	IS61QDP2B41M18C1
Manufacturer	ISSI
File Size	858.94 KB
Description	18Mb QUADP SYNCHRONOUS SRAM
Datasheet	IS61QDP2B41M18C1 Datasheet
Additional preview pages of the IS61QDP2B41M18C1 datasheet.

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Full PDF Text Transcription

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IS61QDP2B41M18C/C1/C2 IS61QDP2B451236C/C1/C2 1Mx18, 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.0 Cycle Read Latency) APRIL 2016 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid Pin (QVLD).  +1.8V core power supply and 1.5, 1.

Published: Feb 18, 2024 |