IS61QDP2B41M18A2 Description
512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations.
IS61QDP2B41M18A2 Key Features
- 512Kx36 and 1Mx18 configuration available
- On-chip Delay-Locked Loop (DLL) for wide data
- Separate independent read and write ports with concurrent read and write operations
- Synchronous pipeline read with late write operation
- Double Data Rate (DDR) interface for read and
- 2.0 cycle read latency
- Fixed 4-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K#) for address and control registering at rising edges only
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data