IS64WV102416BLL Datasheet | ISSI

.. IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL 1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY Features DESCRIPTION ISSI APRIL 2006 ® The ISSI IS61WV102416ALL/BLL and IS64WV102416BLL - High-speed access times: are high-speed, 16M-bit static RAMs organized as 1024K 8, 10, 20 ns words by 16 bits. It is fabricated using ISSI's high-perform- High-performance, low-power CMOS process ance CMOS technology. This highly reliable process coupled - Multiple center power and ground pins for greater with innovative circuit design techniques, yields high-perfornoise immunity mance and low power consumption devices. - Easy memory expansion with CE and OE options When CE is HIGH (deselected), the device assumes a - CE power-down standby mode at which the power dissipation can be reduced down with CMOS input levels. - Fully static operation: no clock or refresh required Easy memory expansion is provided by using Chip Enable - TTL patible inputs and outputs and Output Enable inputs, CE and OE. The active LOW - Single power supply Write Enable (WE) controls both writing and reading of the VDD 1.65V to 2.2V (IS61WV102416ALL) memory. A data byte allows Upper Byte (UB) and Lower speed = 20ns for VDD 1.65V to 2.2V Byte (LB) access. VDD 2.4V to 3.6V (IS61/64WV102416BLL) ee The device is packaged in the JEDEC standard 48-pin speed = 10ns for VDD 2.4V to 3.6V Data Sh TSOP Type I and 48-pin Mini BGA (9mm x 11mm). speed = 8ns for VDD 3.3V + 5% . - Packages available: - 48-ball mini BGA (9mm x 11mm) - 48-pin TSOP (Type I) - Industrial and Automotive Temperature Support - Lead-free available - Data control for upper and lower bytes FUNCTIONAL BLOCK DIAGRAM A0-A19 DECODER 1024K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this...