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ICSSSTV16857 - DDR 14-Bit Registered Buffer

Datasheet Summary

Description

The 14-bit ICSSTV16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels except for the RESET# input which is LVCMOS.

Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#.

Data is triggered on the positive edge of CLK.

Features

  • Differential clock signal.
  • Meets SSTL_2 signal data.
  • Supports SSTL_2 class I & II specifications.
  • low-voltage operation VDD = 2.3V to 2.7V.
  • 48 pin TSSOP package Pin Configuration Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D1 D2 GND VDD D3 D4 D5 D6 D7 CLK# CLK VDD GND.

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Datasheet preview – ICSSSTV16857

Datasheet Details

Part number ICSSSTV16857
Manufacturer Integrated Circuit Systems
File Size 114.68 KB
Description DDR 14-Bit Registered Buffer
Datasheet download datasheet ICSSSTV16857 Datasheet
Additional preview pages of the ICSSSTV16857 datasheet.

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Full PDF Text Transcription

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Integrated Circuit Systems, Inc. ICSSSTV16857 DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • low-voltage operation VDD = 2.3V to 2.
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