ICSSSTV32852 Description
The 24-bit-to-48-bit ICSSSTV32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/ O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous...
ICSSSTV32852 Key Features
- Differential clock signals
- Supports SSTL_2 class II specifications on inputs and outputs
- Low-voltage operation
- VDD = 2.3V to 2.7V
- Available in 114 ball BGA package