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ICSSSTV32852 - DDR 24-Bit to 48-Bit Registered Buffer

Datasheet Summary

Description

The 24-bit-to-48-bit ICSSSTV32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/ O levels, except for the LVCMOS RESET# input.

Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#).

Features

  • Differential clock signals.
  • Supports SSTL_2 class II specifications on inputs and outputs.
  • Low-voltage operation - VDD = 2.3V to 2.7V.
  • Available in 114 ball BGA package. Pin Configuration 1 A B C D E F G H J 2 3 4 5 6 Truth Table RESET# L H H H Notes: 1. 1 K L Inputs CLK X or Floating ↑ ↑ L or H CLK# X or Floating ↓ ↓ L or H D X or Floating H L X Q Outputs Q L H L Q0(2) M N P R T U V W 114-Pin Ball BGA H = "High" Signal Level L = "Low" Signal Level ↑.

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Datasheet Details

Part number ICSSSTV32852
Manufacturer Integrated Circuit Systems
File Size 146.82 KB
Description DDR 24-Bit to 48-Bit Registered Buffer
Datasheet download datasheet ICSSSTV32852 Datasheet
Additional preview pages of the ICSSSTV32852 datasheet.

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Full PDF Text Transcription

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Integrated Circuit Systems, Inc. ICSSSTV32852 www.DataSheet4U.com DDR 24-Bit to 48-Bit Registered Buffer Recommended Application: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signals • Supports SSTL_2 class II specifications on inputs and outputs • Low-voltage operation - VDD = 2.3V to 2.7V • Available in 114 ball BGA package. Pin Configuration 1 A B C D E F G H J 2 3 4 5 6 Truth Table RESET# L H H H Notes: 1.
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