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ICS8305I - MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

General Description

The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-toLVCMOS/LVTTL Fanout Buffer.

The ICS8305I has selectable clock inputs that accept either differential or single ended input levels.

Key Features

  • 4 LVCMOS/LVTTL outputs.
  • Selectable differential or LVCMOS/LVTTL clock inputs.
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
  • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL.
  • Maximum output frequency: 350MHz.
  • Output skew: 40ps (maximum).
  • Part-to-part skew: 700ps (maximum).
  • Additive phase jitter, RMS: 0.04ps (typical).
  • 3.3V core, 3.3V, 2.5V or 1.8V ou.

📥 Download Datasheet

Datasheet Details

Part number ICS8305I
Manufacturer Integrated Device Technology
File Size 203.01 KB
Description MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Datasheet download datasheet ICS8305I Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-toLVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the ICS8305I ideal for those applications demanding well defined performance and repeatability.