IDT5V9910A Datasheet | Integrated Device

IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. MERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK™ JR. Features : - Eight zero delay outputs - <250ps of output to output skew - Selectable positive or negative edge synchronization - Synchronous output enable - Output frequency: 15MHz to 85MHz - 3 skew grades: IDT5V9910A-2: t SKEW0<250ps IDT5V9910A-5: t SKEW0<500ps IDT5V9910A-7: t SKEW0<750ps - 3-level inputs for PLL range control - PLL bypass for DC testing - External feedback, internal loop filter - 12m A balanced drive outputs - Low Jitter: <200ps peak-to-peak - Available in SOIC package DESCRIPTION: The IDT5V9910A is a high fanout phase locked-loop clock driver intended for high performance puting and data-munications applications. It has eight zero delay LVTTL outputs. When the GND/s OE pin is held low, all the outputs are synchronously enabled. However, if GND/s OE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When VCCQ/ PE is held low, all the outputs are synchronized with the negative edge of REF. The FB signal is pared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. FUNCTIONAL BLOCK DIAGRAM VCCQ/PE GND/s OE FB REF Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 The IDT logo is a registered trademark of Integrated Device Technology,...