IDT79R3500 Overview
IDT79R3500 RISC CPU PROCESSOR RISCore ® MILITARY AND MERCIAL TEMPERATURE RANGES RISC CPU PROCESSOR RISCore™ IDT79R3500 Integrated Device Technology, Inc.
IDT79R3500 Key Features
- Efficient Pipelining-The CPU’s 5-stage pipeline design assists in obtaining an execution rate approaching one instructio
- On-Chip Cache Control-The IDT79R3500 provides a high-bandwidth memory interface that handles separate external Instructi
- On-Chip Memory Management Unit-A fully-associative, 64-entry Translation Lookaside Buffer (TLB) provides fast address tr
- Dynamically able to switch between Big- and Little- Endian byte ordering conventions
- Optimizing pilers are available for C, FORTRAN, Pascal, COBOL, Ada, PL/1 and C++
- 20 through 40MHz clock rates yield up to 32VUPS sustained throughput
- Supports independent multi-word block refill of both the instruction and data caches with variable block sizes
- Supports concurrent refill and execution of instructions
- Partial word stores executed as read-modify-write
- 6 external interrupt inputs, 2 software interrupts, with single cycle latency to exception handler routine