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IS43R16160F - 256Mb DDR SDRAM

Download the IS43R16160F datasheet PDF. This datasheet also covers the IS43R83200F variant, as both devices belong to the same 256mb ddr sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

x8 A0-A12 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 DQ7 Data I/O CK, CK System Clock Input CKE Clock Enable CS Chip Select CAS Column Address Strobe Command RAS Row Address Strobe Command WE Write Enable 4 66 VSS 65 DQ7 64 VSSQ 63 N

Key Features

  • DEVICE.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS43R83200F-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS43R16160B 256Mb DDR Synchronous DRAM ISSI
IS43R16160D DDR SDRAM ISSI
IS43R16320F 512Mb DDR SDRAM ISSI
IS43R16400B Four internal banks for concurrent operation ISSI
IS43R32800D DDR SDRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS43R16160 256Mb Synchronous DRAM
IS43R16160A 16Meg x 16 256-MBIT DDR SDRAM
IS43R16320A 32Meg x 16 512-MBIT DDR SDRAM
IS43R16320D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM
IS43R16320E 512Mb DDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS43R83200F IS43/46R16160F, IS43/46R32800F 8Mx32, 16Mx16, 32Mx8 PRELIMINARY INFORMATION 256Mb DDR SDRAM MARCH 2014 FEATURES DEVICE OVERVIEW • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs • Differential clock inputs (CK and CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation • Data Mask for write data.