IS61LV12824 Datasheet | ISSI

128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY Features - High-speed access time: 8, 10 ns - CMOS low power operation - 756 m W (max.) operating @ 8 ns - 36 m W (max.) standby @ 8 ns - TTL patible interface levels - Single 3.3V power supply - Fully static operation: no clock or refresh required - Three state outputs - Available in 119-pin Plastic Ball Grid Array (PBGA) and 100-pin TQFP packages. - Industrial temperature available - Lead-free available ISSI JUNE 2005 ® DESCRIPTION The ISSI IS61LV12824 is a high-speed, static RAM organized as 131,072 words by 24 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. When CE1, CE2 are HIGH and CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE1, CE2, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV12824 is packaged in the JEDEC standard 119-pin PBGA and 100-pin TQFP. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 24 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O23 COLUMN I/O CE2 CE1 CE2 OE WE CONTROL CIRCUIT Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. - 1-800-379-4774 Rev. D...