Datasheet Summary
E n n n n n n n
12.0 V ±5% VPP
28F020 2048K (256K X 8) CMOS FLASH MEMORY n n n n mand Register Architecture for Microprocessor/Microcontroller patible Write Interface Noise Immunity Features
±10% VCC Tolerance Maximum Latch-Up Immunity through EPI Processing ETOX™ Nonvolatile Flash Technology EPROM-patible Process Base High-Volume Manufacturing Experience JEDEC-Standard Pinouts 32-Pin Plastic Dip 32-Lead PLCC 32-Lead TSOP
(See Packaging Spec., Order #231369)
Flash Electrical Chip-Erase 2 Second Typical Chip-Erase Quick-Pulse Programming Algorithm 10 µS Typical Byte-Program 4 second Chip-Program 100,000 Erase/Program Cycles High-Performance Read 90 ns...