CD4071BMS Datasheet PDF - Intersil Corporation CMOS OR Gate Specs

CD4071BMS - CMOS OR Gate

Datasheet Summary

Description

of ‘B’ Series CMOS Devices” A 1 B 2 J=A+B 3 K=C+C 4 C 5 D 6 VSS 7 14 VDD 13 H 12 G 11 M = G + H 10 L = E + F 9 F 8 E CD4072BMS TOP VIEW J=A+B+C+D 1 A 2 B 3 C 4 14 VDD 13 K = E +F + G + H 12 H 11 G 10 F 9 E 8 NC Description CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer

Features

High-Voltage Types (20V Rating).
CD4071BMS Quad 2-Input OR Gate.
CD4072BMS Dual 4-Input OR Gate.
CD4075BMS Triple 3-Input OR Gate.
Medium Speed Operation: - tPHL, tPLH = 60ns (typ) at 10V.
100% Tested for Quiescent Current at 20V.
Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC.
Standardized Symmetrical Output Characteristics.
Noise Margin (Over Full Package Temperatu.

Datasheet Details

Part number	CD4071BMS
Manufacturer	Intersil Corporation
File Size	114.69 KB
Description	CMOS OR Gate
Datasheet	CD4071BMS Datasheet
Additional preview pages of the CD4071BMS datasheet.

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Full PDF Text Transcription

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CD4071BMS, CD4072BMS CD4075BMS December 1992 CMOS OR Gate Pinout CD4071BMS TOP VIEW Features • High-Voltage Types (20V Rating) • CD4071BMS Quad 2-Input OR Gate • CD4072BMS Dual 4-Input OR Gate • CD4075BMS Triple 3-Input OR Gate • Medium Speed Operation: - tPHL, tPLH = 60ns (typ) at 10V • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Standardized Symmetrical Output Characteristics • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No.

Published: Mar 23, 2005 |