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CD4078BMS - CMOS 8 Input NOR/OR Gate

Datasheet Summary

Description

of ‘B’ Series CMOS Devices” CD4078BMS TOP VIEW 14 VDD 13 J 12 H 11 G 10 F 9 E 8 NC J=A+B+C+D+E+F+G+H NC = NO CONNECTION K = A + B + C + D + E + F + G + H Functional Diagram A B C D 2 3 4 5 1 13 E F G H 9 10 11 12 J=A+B+C+D+E+F+G+H K=A+B+C+D+E+F+G+H 6, 8 = NO CONNECTION VDD

Features

  • High Voltage Type (20V Rating).
  • Medium Speed Operation - tPHL, tPLH = 75ns (Typ. ) at VDD = 10V.
  • Buffered Inputs and Output.
  • 5V, 10V and 15V Parametric Ratings.
  • Standardized, Symmetrical Output Characteristics.
  • 100% Tested for Quiescent Current at 20V.
  • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC.
  • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VD.

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Datasheet Details

Part number CD4078BMS
Manufacturer Intersil Corporation
File Size 67.37 KB
Description CMOS 8 Input NOR/OR Gate
Datasheet download datasheet CD4078BMS Datasheet
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CD4078BMS December 1992 CMOS 8 Input NOR/OR Gate Pinout K ** 1 A 2 B 3 C 4 D 5 NC 6 VSS 7 Features • High Voltage Type (20V Rating) • Medium Speed Operation - tPHL, tPLH = 75ns (Typ.) at VDD = 10V • Buffered Inputs and Output • 5V, 10V and 15V Parametric Ratings • Standardized, Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No.
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