CD4096BMS - CMOS Gated J-K Master-Slave Flip-Flops

Product Overview

Intersil Corporation

Datasheet Details

Part number	CD4096BMS
Manufacturer	Intersil Corporation
File Size	101.13 KB
Description	CMOS Gated J-K Master-Slave Flip-Flops
Datasheet	CD4096BMS Datasheet
Additional preview pages of the CD4096BMS datasheet.

Product details

Description

of ‘B’ Series CMOS Devices” CD4095BMS TOP VIEW 14 VDD 13 SET 12 CLOCK 11 K1 10 K2 9 K3 8 Q CD4096BMS TOP VIEW NC 1 RESET 2 J1 3 J2 4 J3 5 Q 6 VSS 7 14 VDD 13 SET 12 CLOCK 11 K1 10 K2 9 K3 8 Q NC = NO CONNECTION Applications Registers Counters Control Circuits SET 3 J1 4 J2 5 J3 12 CLOCK 11 K1 10 K2 9 K3 RESET 13 J CL K 2 Q 6 Q S Q 8 Q Functional Diagrams CD4095BMS Description CD4095BMS and CD4096BMS are J-K Master-Slave FlipFlops featuring separate AND gating

Features

Set-Reset Capability.
High Voltage Types (20V Rating).
CD4095BMS Non-Inverting J and K Inputs.
CD4096BMS Inverting and Non-Inverting J and K Inputs.
16MHz Toggle Rate (Typ. ) at VDD - VSS = 10V.
Gated Inputs.
100% Tested for Quiescent Current at 20V.
5V, 10V and 15V Parametric Ratings.
Standardized Symmetrical Output Characteristics.
Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 1.

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Published: Mar 23, 2005 |