Datasheet4U Logo Datasheet4U.com

HCTS74MS - Radiation Hardened Dual-D Flip-Flop

General Description

The Intersil HCTS74MS is a Radiation Hardened positive edge triggered flip-flop with set and reset.

The HCTS74MS utilizes advanced CMOS/SOS technology to achieve high-speed operation.

This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.

Key Features

  • 3 Micron Radiation Hardened SOS CMOS.
  • Total Dose 200K RAD (Si).
  • SEP Effective LET No Upsets: >100 MEV-cm2/mg.
  • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ).
  • Dose Rate Survivability: >1 x 1012 RAD (Si)/s.
  • Dose Rate Upset >10 10 RAD (Si)/s 20ns Pulse.
  • Latch-Up Free Under Any Conditions.
  • Military Temperature Range: -55oC to +125oC.
  • Significant Power Reduction Compared to LSTTL ICs.
  • DC Op.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HCTS164MS 8-Bit Serial-In/Parallel-Out Shift Register Intersil
HCTS191MS Synchronous 4-Bit Up/Down Counter Intersil
HCTS20MS Radiation Hardened Dual 4-Input NAND Gate Intersil
HCTSM80101AAL High Clearance and Creepage Distance Transformers BOURNS
HCTSM80102AAL High Clearance and Creepage Distance Transformers BOURNS

Other Datasheets by Intersil (now Renesas)

Part Number Description
HCTS74T Radiation Hardened Dual-D Flip-Flop with Set and Reset
HCTS75MS Radiation Hardened Dual 2-Bit Bistable Transparent Latch
HCTS00MS Radiation Hardened Quad 2-Input NAND Gate
HCTS02MS Radiation Hardened Quad 2-Input NOR Gate
HCTS04MS Radiation Hardened Hex Inverter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HCTS74MS September 1995 Radiation Hardened Dual-D Flip-Flop with Set and Reset Pinouts 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-183S CDIP2-T14, LEAD FINISH C TOP VIEW R1 1 D1 2 CP1 3 S1 4 Q1 5 Q1 6 GND 7 14 VCC 13 R2 12 D2 11 CP2 10 S2 9 Q2 8 Q2 Features • 3 Micron Radiation Hardened SOS CMOS • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >10 10 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.