HSP9501 Overview
HSP9501 Data Sheet January 1999 File Number 2786.4 Programmable Data Buffer The HSP9501 is a 10-Bit wide programmable data buffer designed for use in high speed digital systems. Two different modes of operation can be selected through the use of the MODSEL input. In the delay mode, a programmable data pipeline is created which can provide 2 to 1281 clock cycles of delay between the input and output data.
HSP9501 Key Features
- DC to 32MHz Operating Frequency
- Programmable Buffer Length from 2 to 1281 Words
- Supports Data Words to 10-Bits
- Clock Select Logic for Positive or Negative Edge System Clocks
- Data Recirculate or Delay Modes of Operation
- Expandable Data Word Width or Buffer Length
- Three-State Outputs
- TTL patible Inputs/Outputs
- Low Power CMOS
HSP9501 Applications
- DC to 32MHz Operating Frequency
- Programmable Buffer Length from 2 to 1281 Words
- Supports Data Words to 10-Bits
- Clock Select Logic for Positive or Negative Edge System Clocks