Overview: HSP9520, HSP9521
Data Sheet May 1999 File Number
2811.5 Multilevel Pipeline Registers
These devices are multilevel pipeline registers implemented using a low power CMOS process. They are pin for pin compatible replacements for industry standard multilevel pipeline registers such as the L29C520 and L29C521. The HSP9520 and HSP5921 are direct replacements for the AM29520 and AM29521 and WS59520 and WS59521. They consist of four 8-bit registers which are dual ported. They can be configured as a single four level pipeline or a dual two level pipeline. A single 8-bit input is provided, and the pipelining configuration is determined by the instruction code input to the I0 and I1 inputs (see instruction control). The contents of any of the four registers is selectable at the multiplexed outputs through the use of the S0 and S1 multiplexer control inputs (see register select. The output is 8 bits wide and is three-stated through the use of the OE input. The HSP9520 and HSP9521 differ only in the way data is loaded into and between the registers in dual two-level operation. In the HSP9520 when data is loaded into the first level the existing data in the first level is moved to the second level. In the HSP9521 loading the first level simply causes the current data to be overwritten. Transfer of data to the second level is achieved using the single four level mode (I1, I0 = ‘0’). This instruction also causes the first level to be loaded. The HOLD instruction (I1, I0 = ‘1’) provides a means of holding the contents of all registers.
