KK4043B Datasheet | Kodenshi AUK Group

.. TECHNICAL DATA Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS The KK4043B types are quad cross-coupled 3-state CMOS NOR latces. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a mon ENABLE input. A logic “1” or high on the ENABLE input connects the latch states to the Q outputs. A logic “0” or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows mon busing of the outputs. - Operating Voltage Range: 3.0 to 18 V - Maximum input current of 1 µA at 18 V over full package-temperature range; 100 n A at 18 V and 25°C - Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION KK4043BN Plastic KK4043BD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs S X L L H PIN 13 = NO CONNECTION PIN 16=VCC PIN 8= GND H R X L H L H OE L H H H H Outputs Q High Impedance No change L H H X = don’t care .. MAXIMUM RATINGS- Symbol VCC VIN VOUT IIN PD PD Tstg TL - Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±10 750 500 100 -65 to +150 260 Unit V V V m A m W m W °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Remended Operating Conditions. +Derating - Plastic DIP: - 10 m W/°C from 65° to 125°C SOIC Package: : - 7 m W/°C from 65° to 125°C REMENDED OPERATING CONDITIONS Symbol VCC...