LMU112 Datasheet PDF - LOGIC Devices Incorporated 12 x 12-bit Parallel Multiplier Specs

LMU112 - 12 x 12-bit Parallel Multiplier

Datasheet Summary

Description

The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology.

The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K.

Features

u u u u 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned Operands u Three-State Outputs u Package Styles Available:.
48-pin PDIP.
52-pin PLCC, J-Lead LMU112 BLOCK.

Datasheet Details

Part number	LMU112
Manufacturer	LOGIC Devices Incorporated
File Size	46.51 KB
Description	12 x 12-bit Parallel Multiplier
Datasheet	LMU112 Datasheet
Additional preview pages of the LMU112 datasheet.

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Full PDF Text Transcription

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LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier DESCRIPTION The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K. The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A and CLK B). Two’s complement or unsigned magnitude operands are accommodated via the operand control bit (TC) which is loaded along with the B operands. The operands are specified to be in two’s complement format when TC is asserted and unsigned magnitude when TC is deasserted. Mixed mode operation is not allowed.

Published: Apr 25, 2005 |