LMU112 - 12 x 12-bit Parallel Multiplier

LOGIC Devices Incorporated

General Description

The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology.

The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K.

Key Features

u u u u 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned Operands u Three-State Outputs u Package Styles Available:.
48-pin PDIP.
52-pin PLCC, J-Lead LMU112 BLOCK.

📥 Download Datasheet

LMU112 12 x 12-bit parallel multiplier by LOGIC Devices Incorporated - Datasheet Preview

Datasheet Details

Part number	LMU112
Manufacturer	LOGIC Devices Incorporated
File Size	46.51 KB
Description	12 x 12-bit Parallel Multiplier
Datasheet	LMU112 Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
LMU-TK12ASxx	Service Manual	Sanyo
LMUN2110LT1	Bias Resistor Transistors	Leshan Radio Company
LMUN2110LT1G	Bias Resistor Transistors	Leshan Radio Company
LMUN2110LT3G	Bias Resistor Transistors	Leshan Radio Company
LMUN21110LT1	Bias Resistor Transistors	Leshan Radio Company

Other Datasheets by LOGIC Devices Incorporated

Part Number	Description
LMU16	16 x 16-bit Parallel Multiplier
LMU18	16 x 16-bit Parallel Multiplier
LMU08	8 x 8-bit Parallel Multiplier
LMU216	16 x 16-bit Parallel Multiplier
LMU217	16 x 16-bit Parallel multiplier

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier DESCRIPTION The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K. The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A and CLK B). Two’s complement or unsigned magnitude operands are accommodated via the operand control bit (TC) which is loaded along with the B operands. The operands are specified to be in two’s complement format when TC is asserted and unsigned magnitude when TC is deasserted. Mixed mode operation is not allowed.