LMU112 Overview
The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally patible with Fairchilds’s MPY112K. The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A and CLK B).
LMU112 Key Features
- 48-pin PDIP
- 52-pin PLCC, J-Lead