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LMU112 Datasheet

Manufacturer: LOGIC Devices Incorporated
LMU112 datasheet preview

Datasheet Details

Part number LMU112
Datasheet LMU112_LOGICDevicesIncorporated.pdf
File Size 46.51 KB
Manufacturer LOGIC Devices Incorporated
Description 12 x 12-bit Parallel Multiplier
LMU112 page 2 LMU112 page 3

LMU112 Overview

The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally patible with Fairchilds’s MPY112K. The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A and CLK B).

LMU112 Key Features

  • 48-pin PDIP
  • 52-pin PLCC, J-Lead
LOGIC Devices Incorporated logo - Manufacturer

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