DESCRIPTION
CLK, provided either ENA or ENB are LOW. Data present least significant half of the product. at the A inputs, along with the TCA Subsequent truncation of the 16 least control bit, is loaded into the A register significant bits produces a result on the rising edge of CLK. B data and correctly rounded to 16-bit precision. the TCB control bit are similarly loaded. Loading of the A and B At the output, the Right Shift control registers is controlled by the ENA and (RS) selects either of two output formats. ENB controls. When HIGH, these con- RS LOW produces a 31-bit product trols prevent application of the clock to with a copy of the sign bit inserted in the the respective register. The TCA and MSB postion of the least significant half. TCB controls specify the operands as RS HIGH gives a full 32-bit product. Two two’s complement when HIGH, or 16-bit output registers are provided to unsigned magnitude when LOW. hold the most and least significant halves of the result (MSP and LSP) as defined by RS.
LOGIC Devices Incorporated
