LMU217 Datasheet PDF - LOGIC Devices Incorporated 16 x 16-bit Parallel multiplier Specs

LMU217 - 16 x 16-bit Parallel multiplier

Datasheet Summary

Description

The LMU217 is a high-speed, low RND is loaded on the rising edge of power 16-bit parallel multiplier.

CLK, provided either ENA or ENB are LOW.

RND, when HIGH, adds ‘1’ to The LMU217 produces the 32-bit prodthe most significant bit position of the uct of two 16-bit numbers.

Features

u 25 ns Worst-Case Multiply Time u Low Power CMOS Technology u Replaces Cypress CY7C517, IDT 7217L, and AMD Am29517 u Single Clock Architecture with Register Enables u Two’s Complement, Unsigned, or Mixed Operands u Three-State Outputs u 68-pin PLCC, J-Lead LMU217 BLOCK.

Datasheet Details

Part number	LMU217
Manufacturer	LOGIC Devices Incorporated
File Size	178.53 KB
Description	16 x 16-bit Parallel multiplier
Datasheet	LMU217 Datasheet
Additional preview pages of the LMU217 datasheet.

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Full PDF Text Transcription

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LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel multiplier DESCRIPTION The LMU217 is a high-speed, low RND is loaded on the rising edge of power 16-bit parallel multiplier. CLK, provided either ENA or ENB are LOW. RND, when HIGH, adds ‘1’ to The LMU217 produces the 32-bit prodthe most significant bit position of the uct of two 16-bit numbers. Data present least significant half of the product. at the A inputs, along with the TCA Subsequent truncation of the 16 least control bit, is loaded into the A register significant bits produces a result on the rising edge of CLK. B data and correctly rounded to 16-bit precision. the TCB control bit are similarly loaded.

Published: Apr 25, 2005 |