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2096VL - 2.5VIn-SystemProgrammableSuperFASTHighDensityPLD

Datasheet Summary

Description

The ispLSI 2096VL is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP).

The GRP provides complete interconnectivity between all of these elements.

Features

  • SuperFAST HIGH.

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Datasheet preview – 2096VL

Datasheet Details

Part number 2096VL
Manufacturer LatticeSemiconductor
File Size 142.84 KB
Description 2.5VIn-SystemProgrammableSuperFASTHighDensityPLD
Datasheet download datasheet 2096VL Datasheet
Additional preview pages of the 2096VL datasheet.

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Full PDF Text Transcription

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ispLSI 2096VL 2.5V In-System Programmable SuperFAST™ High Density PLD Features • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2096V and 2096VE Devices • 2.5V LOW VOLTAGE 2096 ARCHITECTURE — Interfaces with Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant) — 85 mA Typical Active Current • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 165 MHz Maximum Operating Frequency — tpd = 5.
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