MX25L1006E Datasheet | Macronix

FEATURES 1M-BIT [x 1/x 2] CMOS SERIAL FLASH GENERAL - Serial Peripheral Interface patible -- Mode 0 and Mode 3 - 1,048,576 x 1 bit structure or 524,288 x 2 bits (Dual Output mode) Structure - 32 Equal Sectors with 4K byte each - Any Sector can be erased individually - 2 Equal Blocks with 64K byte each - Any Block can be erased individually - Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations - Latch-up protected to 100m A from -1V to Vcc +1V PERFORMANCE - High Performance - Fast access time: 104MHz serial clock - Serial clock of Dual Output mode: 80MHz - Fast program time: 0.6ms(typ.) and 3ms(max.)/page (256-byte per page) - Byte program time: 9us (typ.) - Fast erase time: 40ms(typ.)/sector (4K-byte per sector) ; 0.8s(typ.) and 2s(max.)/chip - Low Power Consumption - Low active read current: 12m A(max.) at 104MHz and 4m A(max.) at 33MHz - Low active programming current: 15m A (typ.) - Low active sector erase current: 9m A (typ.) - Low standby current: 15u A (typ.) - Deep power-down mode 2u A (typ.) - Minimum 100,000 erase/program cycles - 20 years data retention SOFTWARE FEATURES - Input Data Format - 1-byte mand code - Block Lock protection - The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase instructions. - Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) - Status Register Feature - Electronic Identification - JEDEC 2-byte Device ID - RES mand, 1-byte Device ID - Support Serial Flash Discoverable Parameters (SFDP)...