SY100S301 Datasheet | Micrel Semiconductor

Micrel, Inc. TRIPLE 5-INPUT OR/NOR GATE Features DESCRIPTION s Max. propagation delay of 750ps s IEE min. of - 25m A s Industry standard 100K ECL levels s Extended supply voltage option: VEE = - 4.2V to - 5.5V s Voltage and temperature pensation for improved noise immunity s 20% faster than Fairchild 300K at lower power s Internal 75kΩ input pull-down resistors s Function and pinout patible with Fairchild F100K s Available in 28-pin PLCC package The SY100S301 is an ultra-fast triple 5-input OR/NOR gate designed for use in high-performance ECL systems. The inputs on this device have 75kΩ pull-down resistors. BLOCK DIAGRAM D1a D2a D3a D4a D5a D1b D2b D3b D4b D5b D1c D2c D3c D4c D5c Oa Oa Ob Ob Oc Oc PIN NAMES Pin Dna, Dnb, Dnc Oa, Ob, Oc Oa, Ob, Oc VEES VCCA Function Data Inputs (n-1...5) Data Outputs plementary Data Outputs VEE Substrate VCCO for ECL Outputs M9999-042307 hbwhelp@micrel. or (408) 955-1690 Rev.: H Amendment: /0 Issue Date: April 2007 Micrel, Inc. PACKAGE/ORDERING INFORMATION D4a D3a D2a VEES D1a Oa Oa Ordering Information 11 10 9 8 7 6 5 Part Number Package...