SY100S317 Datasheet | Micrel Semiconductor

Micrel, Inc. TRIPLE 2-WIDE OA/OAI GATE Features DESCRIPTION s Max. propagation delay of 900ps s IEE min. of - 48m A s Extended supply voltage option: VEE = - 4.2V to - 5.5V s Voltage and temperature pensation for improved noise immunity s Internal 75kΩ input pull-down resistors s Approximately 40% lower power than Fairchild s Function and pinout patible with Fairchild F100K s Available in 28-pin PLCC package The SY100S317 is a set of ultra-fast, triple 2-wide OR/ AND gates designed for use in high-performance ECL systems. This device offers both true and plement outputs. The inputs on this device have 75kΩ pull-down resistors. BLOCK DIAGRAM Ea D1a D2a D3a D4a Eb D1b D2b D3b D4b Ec D1c D2c D3c D4c PIN NAMES Pin Function Dna - Dnc Data Inputs (n = 1...4) Ea - Ec Enable Inputs Oa Oa - Oc Data Outputs Oa Oa - Oc plementary Data Outputs VEES VEE...