Download SY100S317 Datasheet PDF
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SY100S317 Description

propagation delay of 900ps s IEE min. of 48mA s Extended supply voltage option: VEE = 4.2V to 5.5V s Voltage and temperature pensation for improved noise immunity s Internal 75kΩ input pull-down resistors s Approximately 40% lower power than Fairchild s Function and pinout patible with Fairchild F100K s Available in 28-pin PLCC package The SY100S317 is a set of ultra-fast, triple 2-wide OR/ AND gates designed for...

SY100S317 Key Features

  • 0.95V -1.69V