SY100S863 Datasheet | Micrel Semiconductor

Micrel, Inc. NOT REMENDED FOR NEW DESIGNS 8-INPUT PECL DIFFERENTIAL MUX WITH TTL SELECTS Features s Low skew s Differential PECL inputs s Differential cut-off PECL outputs capable of driving 25Ω load for driving data bus s Tri-state TTL output s TTL select and enable input s Internal 75KΩ PECL input pull-down resistors s PECL I/O fully patible with industry standard s Available in 28-pin PLCC package DESCRIPTION The SY100S863 is a PECL 8:1 multiplexer designed for use in new, high-performance PECL systems. It has differential PECL outputs and a standard TTL output. The TTL select inputs (SEL0, SEL1, SEL2) determine which one of the eight differential PECL data inputs (D0- D7) is propagated to the outputs. The enable pin, EN, is provided for expansion. When EN is at a TTL logic one level, both PECL and TTL outputs are enabled. When the enable pin is set to TTL logic zero level, both PECL outputs of the differential pair are in cut-off and the TTL output is in a three-state condition. BLOCK DIAGRAM D0 (4) D0 (5) D1 (6) D1 (7) D2 (8) D2 (9) D3 (10) D3 (11) D4 (27) D4 (26) D5 (25) D5 (24) D6 (23) D6 (22) D7 (21) D7 (20) 8:1 MUX (17) Q (18) Q (13) QTTL PIN NAMES Pin D0, /D0 - D7, /D7 Q, /Q QTTL EN SEL0,1,2 Function Differential PECL Input Pairs Differential PECL Outputs TTL Output Enable Input Select Inputs 8 DIFFERENTIAL PECL INPUTS EN (15) SEL0 (28) SEL1 (2) SEL2 (3) TTL INPUTS M9999-032406 hbwhelp@micrel. or (408) 955-1690 Rev.: G Amendment: /0 Issue Date: March 2006 Micrel, Inc. PACKAGE/ORDERING INFORMATION D5 D5 D6 D6 D7 D7...