SY100S891 Description
s 25Ω cut-off bus outputs s 50Ω receiver outputs s Transmit and receive registers with separate clocks s 1500ps max. delay from CLK1 to Bus Outputs (BUS) s 1500ps max. delay from CLK2 to Receiver Outputs (Q) s Individual bus enable pins s Internal 75KΩ input pull-down resistors s Voltage and temperature pensation for improved noise immunity s Industry standard 100K ECL levels s Extended supply voltage option:.
SY100S891 Key Features
- BUS4) are specified for driving a 25 ohm bus and the receive outputs (Q0
- Q4) are specified for driving a 50 ohm line. The bus outputs have a normal high level output voltage and a normal low le
- BUSEN4) is high. However, the output is switched to a cut-off level when a bus-enable is low. This cut-off level is suff
- D4 CLK1 CLK2 MR Q0
- Q4 BUS0-4