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SY10E150 - 6-BIT D LATCH

Download the SY10E150 datasheet PDF. This datasheet also covers the SY100E150 variant, as both devices belong to the same 6-bit d latch family and are provided as variant models within a single manufacturer datasheet.

Description

The SY10/100E150 are 6-bit D latches with differential outputs designed for use in new, high- performance ECL systems.

When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output.

Features

  • s 700ps max. propagation delay s Extended 100E VEE range of.
  • 4.2V to.
  • 5.5V s Differential outputs s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75KΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E150 s Available in 28-pin PLCC package BLOCK.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SY100E150_MicrelSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number SY10E150
Manufacturer Micrel Semiconductor
File Size 58.00 KB
Description 6-BIT D LATCH
Datasheet download datasheet SY10E150 Datasheet

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Other Datasheets by Micrel Semiconductor

Part Number Description
SY10E151 6-BIT D REGISTER
SY10E154 5-BIT 2:1 MUX-LATCH
SY10E155 6-BIT 2:1 MUX-LATCH
SY10E156 3-BIT 4:1 MUX-LATCH
SY10E157 QUAD 2:1 MULTIPLEXER

Full PDF Text Transcription

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Micrel, Inc. 6-BIT D LATCH SY10E150 SY1S0YE10105E0150 SY100E150 FEATURES s 700ps max. propagation delay s Extended 100E VEE range of –4.2V to –5.5V s Differential outputs s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75KΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E150 s Available in 28-pin PLCC package BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 LEN1 LEN2 MR D R D R D R D R D R D R Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 DESCRIPTION The SY10/100E150 are 6-bit D latches with differential outputs designed for use in new, high- performance ECL systems. When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output.
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