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SY10E156 - 3-BIT 4:1 MUX-LATCH

Download the SY10E156 datasheet PDF. This datasheet also covers the SY100E156 variant, as both devices belong to the same 3-bit 4:1 mux-latch family and are provided as variant models within a single manufacturer datasheet.

Description

The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems.

The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latches.

Features

  • s s s s s s s 900ps max. D to output Extended 100E VEE range of.
  • 4.2V to.
  • 5.5V 800ps max. LEN to output Differential outputs Asynchronous Master Reset Dual latch enables Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75KΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E156 s Available in 28-pin PLCC package.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SY100E156_MicrelSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number SY10E156
Manufacturer Micrel Semiconductor
File Size 60.88 KB
Description 3-BIT 4:1 MUX-LATCH
Datasheet download datasheet SY10E156 Datasheet

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Other Datasheets by Micrel Semiconductor

Part Number Description
SY10E150 6-BIT D LATCH
SY10E151 6-BIT D REGISTER
SY10E154 5-BIT 2:1 MUX-LATCH
SY10E155 6-BIT 2:1 MUX-LATCH
SY10E157 QUAD 2:1 MULTIPLEXER

Full PDF Text Transcription

Click to expand full text
3-BIT 4:1 MUX-LATCH SY10E156 SY100E156 FEATURES s s s s s s s 900ps max. D to output Extended 100E VEE range of –4.2V to –5.5V 800ps max. LEN to output Differential outputs Asynchronous Master Reset Dual latch enables Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75KΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E156 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latches.
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