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ML6510 - Series Programmable Adaptive Clock Manager (PACMan)

General Description

The ML6510 (Super PACMan™) is a Programmable Adaptive Clock Manager which offers an ideal solution for managing high speed synchronous clock distribution in next generation, high speed personal computer and workstation system designs.

Key Features

  • s s Input clocks can be either TTL or PECL with low input to output clock phase error 8 independent, automatically deskewed clock outputs with up to 5ns of on-board deskew range (10ns round trip) Controlled edge rate TTL-compatible CMOS clock outputs capable of driving 40Ω PCB traces 10 to 80MHz (6510-80) or 10 to 130MHz (6510-130) input and output clock frequency range Less than 500ps skew between inputs at the device loads Small-swing reference clock outputs for minimizing part-to-part skew F.

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Datasheet Details

Part number ML6510
Manufacturer Micro Linear
File Size 603.94 KB
Description Series Programmable Adaptive Clock Manager (PACMan)
Datasheet download datasheet ML6510 Datasheet

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March 1997 ML6510* Series Programmable Adaptive Clock Manager (PACMan™) GENERAL DESCRIPTION The ML6510 (Super PACMan™) is a Programmable Adaptive Clock Manager which offers an ideal solution for managing high speed synchronous clock distribution in next generation, high speed personal computer and workstation system designs. It provides eight channels of deskew buffers that adaptively compensate for clock skew using only a single trace. The input clock can be either TTL or PECL, selected by a bit in the control register. Frequency multiplication or division is possible using the M&N divider ratio, within the maximum frequency limit. 0.5X, 1X, 2X and 4X clocks can be easily realized. The ML6510 is implemented using a low jitter PLL with on-chip loop filter.