SY100ELT22 Datasheet | Microchip Technology

Dual TTL-to-Differential PECL Translator Features - 300 ps Typical Propagation Delay - <100 ps Output-to-Output Skew - Differential PECL Outputs - PNP TTL Inputs for Minimal Loading - Flow-Through Pinouts - Available in 8-Lead SOIC Package General Description The SY100ELT22 is a dual TTL-to-differential PECL translator. Because positive ECL (PECL) levels are used, only +5V and ground is required. The small outline 8-lead SOIC package and the low-skew, dual-gate design of the SY100ELT22 makes it ideal for applications that require the translation of a clock and a data signal. The SY100ELT22 is patible with positive ECL 100K logic levels. Package Type SY100ELT22 8-Lead SOIC Q0 1 /Q0 2 PECL Q1 3 /Q1 4 8 VCC 7 D0 TTL 6 D1 5 GND  2018 Microchip Technology Inc. DS20005996A-page 1 1.0 ELECTRICAL CHARACTERISTICS...