MT46V32M4 Overview
m 128Mb: x4, x8, x16 DDR SDRAM.
MT46V32M4 Key Features
- 4 Meg x 8 x 4 Banks MT46V16M8 a MT46V8M16 at
- 2 Meg x 16 x 4 Banks .D w w Features Options Marking w
- VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
- VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR 400)
- Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two
- one per byte)
- Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
- Differential clock inputs (CK and CK#)
- mands entered on each positive CK edge
- DQS edge-aligned with data for READs; centeraligned with data for WRITEs