MT49H32M9 Datasheet | Micron Technology

Features Features - 533 MHz DDR operation (1.067 Gb/s/pin data rate) - 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) - Organization - 32 Meg x 9, 16 Meg x 18, and 8 Meg x 36 - 8 internal banks for concurrent operation and maxi- mum bandwidth - Reduced cycle time (15ns at 533 MHz) - Nonmultiplexed addresses (address multiplexing option available) - SRAM-type interface - Programmable READ latency (RL), row cycle time, and burst sequence length - Balanced READ and WRITE latencies in order to optimize data bus utilization - Data mask for WRITE mands - Differential input clocks (CK, CK#) - Differential input data clocks (DKx, DKx#) - On-die DLL generates CK edge-aligned data and output data clock signals - Data valid signal (QVLD) - 32ms refresh (8K refresh for each bank; 64K refresh...