Datasheet Summary
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM MT4LC4M4E8, MT4C4M4E8 MT4LC4M4E9, MT4C4M4E9
DRAM
Features
- Industry-standard x4 pinout, timing, functions and packages
- State-of-the-art, high-performance, low-power CMOS silicon-gate process
- Single power supply (+3.3V ±0.3V or +5V ±10%)
- All inputs, outputs and clocks are TTL-patible
- Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR)
- Optional Self Refresh (S) for low-power data retention
- 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh)
- Extended Data-Out (EDO) PAGE MODE access cycle
- 5V-tolerant inputs and I/Os on 3.3V devices
PIN ASSIGNMENT (Top View) 24/26-Pin SOJ (DA-2)
VCC DQ1 DQ2 WE#...