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MT54W2MH18B - SRAM 2-WORD BURST

This page provides the datasheet information for the MT54W2MH18B, a member of the MT54W4MH8B SRAM 2-WORD BURST family.

Datasheet Summary

Description

4 Meg x 8, QDRIIb2 FBGA 4 Meg x 9, QDRIIb2 FBGA 2 Meg x 18, QDRIIb2 FBGA 1 Meg x 36, QDRIIb2 FBGA OPTIONS Clock Cycle Timing 4ns (250 MHz) 5ns (200 MHz) 6ns (167 MHz) 7.5ns (133 MHz) Configurations 4 Meg x 8 4 Meg x 9 2 Meg x 18 1 Meg x 36 Package 165-ball, 15mm x 17mm

Features

  • DLL circuitry for accurate output data placement MT54W4MH8B MT54W4MH9B MT54W2MH18B MT54W1MH36B Figure 1 165-Ball FBGA.
  • Separate independent read and write data ports with concurrent transactions.
  • 100 percent bus utilization DDR READ and WRITE operation.
  • Fast clock to valid data times.
  • Full data coherency, providing most current data.
  • Two-tick burst counter for low DDR transaction size.
  • Double data rate operation on read and write.

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Datasheet preview – MT54W2MH18B

Datasheet Details

Part number MT54W2MH18B
Manufacturer Micron Technology
File Size 567.42 KB
Description SRAM 2-WORD BURST
Datasheet download datasheet MT54W2MH18B Datasheet
Additional preview pages of the MT54W2MH18B datasheet.

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Full PDF Text Transcription

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ADVANCE‡ www.DataSheet4U.com 4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.
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