MT44K32M18 Datasheet | Micron Technology

Features RLDRAM 3 - 2 Meg x 18 x 16 Banks MT44K16M36 - 1 Meg x 36 x 16 Banks Features - 1066 MHz DDR operation (2133 Mb/s/ball data rate) - 76.8 Gb/s peak bandwidth (x36 at 1066 MHz clock frequency) - Organization - 32 Meg x 18, and 16 Meg x 36 mon I/O (CIO) - 16 banks - 1.2V center-terminated push/pull I/O - 2.5V VEXT, 1.35V VDD, 1.2V VDDQ I/O - Reduced cycle time (t RC (MIN) = 7.5 - 12ns) - SDR addressing - Programmable READ/WRITE latency (RL/WL) and burst length - Data mask for WRITE mands - Differential input clocks (CK, CK#) - Free-running differential input data clocks (DKx, DKx#) and output data clocks (QKx, QKx#) - On-die DLL generates CK edge-aligned data and differential output data clock signals - 64ms refresh (128K refresh per 64ms) - 168-ball BGA package - Ω or 60Ω matched impedance outputs - Integrated on-die termination (ODT) - Single or multibank writes - Extended operating range (200- 1066 MHz) - READ training register - Multiplexed and non-multiplexed addressing capa- bilities - Mirror function - Output driver and ODT calibration - JTAG interface (IEEE 1149.1-2001) Options1 - Clock cycle and t RC timing - 0.93ns and t RC (MIN) = 7.5ns (RL3-2133) - 0.93ns and t RC (MIN) = 8ns (RL3-2133) - 1.07ns and t RC (MIN) =...