MT44K32M36 Datasheet | Micron Technology

Features RLDRAM 3 MT44K64M18 - 4 Meg x 18 x 16 Banks MT44K32M36 - 2 Meg x 36 x 16 Banks Features - 1200 MHz DDR operation (2400 Mb/s/ball data rate) - 86.4Gb/s peak bandwidth (x36 at 1200 MHz clock frequency) - Organization - 64 Meg x 18, and 32 Meg x 36 mon I/O (CIO) - 16 banks - 1.2V center-terminated push/pull I/O - 2.5V VEXT, 1.35V VDD, 1.2V VDDQ (optional 1.35V VDDQ for 2400 operation only). - Reduced cycle time (t RC (MIN) = 6.67 - 8ns) - SDR addressing - Programmable READ/WRITE latency (RL/WL) and burst length - Data mask for WRITE mands - Differential input clocks (CK, CK#) - Free-running differential input data clocks (DKx, DKx#) and output data clocks (QKx, QKx#) - On-die DLL generates CK edge-aligned data and differential output data clock signals - 64ms refresh (128K refresh per 64ms) - 168-ball BGA package - Ω or 60Ω matched impedance outputs - Integrated on-die termination (ODT) - Single...