Datasheet4U Logo Datasheet4U.com

M5M4V16169DTP-8 - 16M (1M-WORD BY 16-BIT) CACHED DRAM

Download the M5M4V16169DTP-8 datasheet PDF. This datasheet also covers the M5M4V16169DTP variant, as both devices belong to the same 16m (1m-word by 16-bit) cached dram family and are provided as variant models within a single manufacturer datasheet.

Description

1.

The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single monolithic circuit.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M5M4V16169DTP_MitsubishiElectricSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
M5M417800AJ Fast Page Mode 16M-Bit DRAM Mitsubishi Electric
M5M417800CJ Fast Page Mode 16M-Bit DRAM Mitsubishi Electric
M5M417800DJ Fast Page Mode 16M-Bit DRAM Mitsubishi Electric
M5M417805CJ Hyper Page Mode 16M-Bit DRAM Mitsubishi Electric
M5M417805DJ EDO Mode 16M-Bit DRAM Mitsubishi Electric

Other Datasheets by Mitsubishi Electric

Part Number Description
M5M4V16169DTP-10 16M (1M-WORD BY 16-BIT) CACHED DRAM
M5M4V16169DTP-15 16M (1M-WORD BY 16-BIT) CACHED DRAM
M5M4V16169DTP-7 16M (1M-WORD BY 16-BIT) CACHED DRAM
M5M4V16169DTP 16M (1M-WORD BY 16-BIT) CACHED DRAM
M5M4V16169DRT-10 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Preliminary This document is a preliminary Target Spec. and some of the contents are subject to change without notice. DESCRIPTION PINCONFIGURATION (TOP VIEW) 1. The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single monolithic circuit. The block data transfer between the DRAM and the data transfer buffers (RB1/RB2/WB1/WB2) is performed in one instruction cycle, a fundamental advantage over a conventional DRAM/SRAM cache.
Published: |