M5M4V16169DTP - 16M (1M-WORD BY 16-BIT) CACHED DRAM

Description

1.

The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single monolithic circuit.

Features

• Type name M5M4V16169TP/RT-7 M5M4V16169TP/RT-8 M5M4V16169TP/RT-10 M5M4V16169TP/RT-15 SRAM Access/cycle 5.6ns/7ns 6.4ns/8ns 8.0ns/10ns 8.0ns/15ns DRAM Access/cycle 49ns/70ns 56ns/80ns 60ns/90ns 75ns/120ns Power Dissipation (Typ) DRAM: 530 SRAM: 860 DRAM: 500 SRAM: 800 DRAM: 430 SRAM: 660 DRAM: 330 SRAM: 420 Package code:70P3S-L Vss Ad9 Ad8 Ad7 Ad11 Ad10 As9 As8 As7 As6 DQ15 Vss DQ14 DQ13 VccQ DQ12 Vcc 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38.