M5M54R08AJ-15 Datasheet | Mitsubishi Electric

MITSUBISHI LSIs 1998.11.30 Ver..B PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change M5M54R08AJ-10,-12,-15 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M54R08AJ is a family of 524288-word by 8-bit static RAMs, fabricated with the high performance CMOS silicon gate process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL patible. They include a power down feature as well. Features - Fast access time M5M54R08AJ-10 ... 10ns(max) M5M54R08AJ-12 ... 12ns(max) M5M54R08AJ-15 ... 15ns(max) - Single +3.3V power supply - Fully static operation : No clocks, No refresh - mon data I/O - Easy memory expansion by S - Three-state outputs : OR-tie capability - OE prevents data contention in the I/O bus - Directly TTL patible : All inputs and outputs A0 A1 address A2 inputs A3 A4 chip select S input data inputs/ DQ1 outputs DQ2 (3.3V) VCC (0V) GND data DQ3 inputs/ outputs DQ4 write control W input A5 A6 address A7 inputs A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 address inputs A16 A15 output enable OE input data DQ8 inputs/ DQ7 outputs GND (0V) VCC (3.3V) DQ6 data inputs/ DQ5 outputs A14 A13 A12 A11 address inputs A10 NC Outline 36P0K (SOJ) APPLICATION High-speed memory units PACKAGE M5M54R08AJ : 36pin 400mil SOJ BLOCK DIAGRAM A0 A1 A2 address A4...