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MCM69F536C - 32K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

General Description

Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycle.

chip deselect does not occur when ADSP is

Key Features

  • r>.
  • 55 to 125 Unit V V mA W °C °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MCM69F618C 64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69F536C/D 32K x 36 Bit Flow–Through BurstRAM Synchronous Fast Static RAM The MCM69F536C is a 1M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, 486, i960™, and Pentium™ microprocessors. It is organized as 32K words of 36 bits each. This device integrates input registers, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.