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MCM69F618C - 64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

General Description

Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE or chip deselect cycle.

chip deselect does not occur when ADSP is as

Key Features

  • dvised that normal precautions be taken to avoid.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

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Full PDF Text Transcription (Reference)

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69F618C/D 64K x 18 Bit Flow–Through BurstRAM Synchronous Fast Static RAM The MCM69F618C is a 1M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, 486, i960™, and Pentium™ microprocessors. It is organized as 64K words of 18 bits each. This device integrates input registers, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.