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MCM69T618 - 64K x 18 Bit Synchronous Pipelined Cache Tag RAM

Description

Pin Locations 42 8, 9, 12, 13, 18, 19, 22, 23, 24, 58, 59, 62, 63, 68, 69, 72, 73, 74 86 Symbol DE DQ1

DQ18 Type Input I/O Description Data Enable Input: Latched on the rising clock edge, active low.

The data input register is only updated when DE is low.

Features

  • MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance Symbol Cin CI/O Min.
  • Typ 3 6 Max 5 8 Unit pF pF MCM69T618 6.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69T618/D 64K x 18 Bit Synchronous Pipelined Cache Tag RAM The MCM69T618 is a 1M–bit synchronous fast static RAM with integrated tag compare function. It is designed to address tag RAM for 512KB, 1MB, or 2MB secondary cache as well as to be used as a data RAM for 512KB caches. This device is organized as 64K words of 18 bits each. It integrates input registers, output registers, tag comparators, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache tag RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
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