MCM72BA64 - 256KB and 512KB BurstRAM Secondary Cache

Motorola Semiconductor (now NXP Semiconductors)

Download the MCM72BA64 datasheet PDF. This datasheet also covers the MCM72BA32 variant, as both devices belong to the same 256kb and 512kb burstram secondary cache family and are provided as variant models within a single manufacturer datasheet.

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MCM72BA64 256kb and 512kb burstram secondary cache by Motorola Semiconductor (now NXP Semiconductors) - Datasheet Preview — Note: The manufacturer provides a single datasheet file (MCM72BA32_MotorolaInc.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number	MCM72BA64
Manufacturer	Motorola Semiconductor (now NXP Semiconductors)
File Size	237.37 KB
Description	256KB and 512KB BurstRAM Secondary Cache
Datasheet	MCM72BA64 Datasheet

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number	Description
MCM72BA32	256KB and 512KB BurstRAM Secondary Cache
MCM72BB32	256KB and 512KB BurstRAM Secondary Cache
MCM72BB64	256KB and 512KB BurstRAM Secondary Cache
MCM72BF32	256KB and 512KB BurstRAM Secondary Cache
MCM72BF64	256KB and 512KB BurstRAM Secondary Cache

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA 256KB and 512KB BurstRAM™ Secondary Cache Module for Pentium™ The MCM72BA32SG and MCM72BA64SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor. The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses four of Motorola’s MCM67B518 or MCM67B618 BiCMOS BurstRAMs. Bursts can be initiated with either address status processor (ADSP) or address status controller (ADSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst advance (ADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control.