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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
256KB and 512KB BurstRAM™ Secondary Cache Module for Pentium™
The MCM72BA32SG and MCM72BA64SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor. The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses four of Motorola’s MCM67B518 or MCM67B618 BiCMOS BurstRAMs.
Bursts can be initiated with either address status processor (ADSP) or address status controller (ADSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst advance (ADV) input pin.
Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control.
MCM72BA64 Datasheet
