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MPC950 - (MPC950 / MPC951) LOW VOLTAGE PLL CLOCK DRIVER

Download the MPC950 datasheet PDF. This datasheet also covers the MPC951 variant, as both devices belong to the same (mpc950 / mpc951) low voltage pll clock driver family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • allow for the MPC951 to be used as a zero delay, low skew fanout buffer. In addition, the external feedback allows for a wider variety of input.
  • to.
  • output frequency relationships. The MPC951 REF_SEL pin allows for the selection of an alternate LVCMOS input clock to be used as a test clock or to provide the reference for the PLL from an LVCMOS source. The MPC950 provides an external test clock input for scan clock distribution or system diagnostics. In addition the REF_SEL pin allo.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MPC951_Motorola.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
MPC958 LOW VOLTAGE PLL CLOCK DRIVER Motorola Inc
MPC9109 Low Voltage 1:18 Clock Distribution Chip Integrated Device Technology
MPC9230 800MHz Low Voltage PECL Clock Synthesizer IDT
MPC9239 900 MHz Low Voltage LVPECL Clock Synthesizer Freescale Semiconductor
MPC92432 1360 MHz Dual Output LVPECL Clock Synthesizer IDT

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MPC951 (MPC950 / MPC951) LOW VOLTAGE PLL CLOCK DRIVER
MPC952 LOW VOLTAGE PLL CLOCK DRIVER
MPC953 LOW VOLTAGE PLL CLOCK DRIVER
MPC954 LOW VOLTAGE PLL CLOCK DRIVER
MPC9100 DUAL PLL CLOCK GENERATOR

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC950/951 are 3.3V compatible, PLL based clock driver devices targeted for high performance clock tree designs. With output frequencies of up to 180MHz and output skews of 375ps the MPC950 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle–to–cycle and long term jitter. This parameter is of significant importance when the clock driver is providing the reference clock for PLL’s on board today’s microprocessors and ASiC’s. The devices offer 9 low skew outputs, the outputs are configurable to support the clocking needs of the various high performance microprocessors. www.DataSheet4U.